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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. december 2008 rev 3 1/29 1 nand32gah0h nand64gah0h 4-gbyte, 8-gbyte, 1.8 v/3.3 v supply, nand flash memories with multimediacard? interface features packaged nand flash memory with multimediacard interface up to 8 gbytes of formatted data storage high capacity memory access emmc/multimediacard system specification, compliant with v4.3 full backward compatibility with previous multimediacard system specification bus mode ? high-speed multimediacard protocol ? three different data bus widths:1 bit, 4 bits, 8 bits ? data transfer rate: up to 52 mbyte/s operating voltage range: ?v ccq =1.8 v/3.3 v ?v cc = 3.3 v multiple block read (x8 at 52 mhz): up to 29 mbyte/s multiple block write (x8 at 52 mhz): up to 11 mbyte/s power dissipation ? standby current: down to 200 a (typ) ? read current: down to 40 ma (typ) ? write current: down to 100 ma (typ) error free memory access ? internal error correction code ? internal enhanced data management algorithm (wear levelling, bad block management, garbage collection) ? possibility for the host to make sudden power failure safe-update operations for data content security ? password protection of data ? built-in write protection boot ? simple boot sequence method power saving ? enhanced power saving method by introducing sleep functionality fbga lfbga169 12 x 16 x 1.4 mm (za) table 1. device summary root part number package operating voltage nand32gah0h lfbga169 v cc =3.3v, v ccq =1.8v/3.3v nand64gah0h www.numonyx.com
contents nand32gah0 h, nand64gah0h 2/29 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 emmc standard specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 product specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 device physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 memory array partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 multimediacard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.1 clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.2 command (cmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.3 input/outputs (dat0-dat7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.4 v cc core supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.5 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.6 v ccq input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.7 v ssq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 bus operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6 bus signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.7 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 high speed multimediacard operati on . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 data transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
nand32gah0h, nand6 4gah0h contents 3/29 6.5 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.7 state transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.8 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.9 timing diagrams and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.10 minimum performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 device registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 operation conditions register (ocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 card identification (cid) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 card specific data register (csd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 extended csd register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5 rca (relative card address) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.6 dsr (driver stage register) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.7 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
list of tables nand3 2gah0h, nand64gah0h 4/29 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. system performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. communication channel performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. ocr register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. card identification (cid) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. card specific data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. extended csd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. lfbga169 12 x 16 x 1.4 mm 132+21+16 3r14 0.50 mm, package mechanical data . . . . 26 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
nand32gah0h, nand64gah0 h list of figures 5/29 list of figures figure 1. device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. lfbga169 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. memory array structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. lfbga169 12 x 16 x 1.4 mm 132+21+16 3r14 0.50 mm, package outline . . . . . . . . . . . 25
description nand32g ah0h, nand64gah0h 6/29 1 description the nandxxxah0h is an embedded flash memo ry storage solution with multimediacard ? interface (emmc ? ). the emmc ? was developed for universal low cost data storage and communication media. the nandxxxah0h is fully compatible with mmc bus and hosts. the nandxxxah0h communications are made through an advanced 13-pin bus. the bus can be either 1-bit, 4-bit, or 8-bit in width. the device operates in high-speed mode at clock frequencies equal to or higher than 20 mhz, which is the mmc standard. the communication protocol is defined as a part of this mmc standard and referred to as multimediacard mode. the device is designed to cover a wide area of applications such as smart phones, cameras, organizers, pda, digital recorders, mp3 players, pagers, electronic toys, etc. they feature high performance, low power consumption, low cost and high density. to meet the requirements of embedded high density storage media and mobile applications, the nandxxxah0h supports both 3.3 v supply voltage (v cc ), and 1.8 v/3.3 v input/output voltage (v ccq ). the address argument for the nandxxxah0h is the sector address (512-byte sectors) instead of the byte address. this means that nandxxxah0h is not backward compatible with devices of density lower than 2 gbytes. if there is no indication by the host to the memory that the host is capable of handling sector type of addressing, the nandxxxah0h will change its state to inactive. the device has a built-in in telligent controller which manage s interface prot ocols, data storage and retrieval, wear leveling, bad block management, garbage collection, and internal ecc. the nandxxxah0h makes available to the host sudden power failure safe-update operations for the data content, by supporting reliable write features. the device supports boot operation and sleep/awake commands. in particular, during the sleep state the host power regulator for v cc can be switched off, thus minimizing the power consumption of the nandxxxah0h. the system performance and characteristics are given in ta bl e 2 , ta bl e 3 , and ta bl e 4 . 1.1 emmc standard specification the nandxxxah0h device is fully compatible with the jedec standard specification no. jesd84-a43. this datasheet describes the key and specific features of the nandxxxah0h device. any additional information required to interface the device to a host system and all the practical methods for card detection and access can be found in the proper sections of the jedec standard specification.
nand32gah0h, nand64gah0h product specification 7/29 2 product specification 2.1 system performance table 2. system performance system performance typical value (1) unit nand32gah0h, nand64gah0h multiple block read sequential (2) 29 mbyte/s multiple block read 64-kbyte chunk (3) 19 mbyte/s multiple block write sequential (2) 11 mbyte/s multiple block write 64-kbyte chunk (3) 5mbyte/s 1. values given for an 8-bit bus widt h, a clock frequency of 52 mhz, v cc = 3.3 v and v ccq =1.8v. 2. based on a 4-mbyte file transfer. 3. test performed by writing/reading a 64-kbyte chunk of dat a to/from random logical addresse s (aligned to physical block boundaries) of the card. the performance is calculat ed as an average out of several 64-kbyte accesses. table 3. current consumption operation test conditions current consumption (1) unit nand32gah0h nand64gah0h typ max typ max read v cc = 3.3 v 5% v ccq =1.8v5% 40 80 40 80 ma write 100 150 100 150 standby v cc = 3.3 v 5% 20 40 a v ccq = 1.8 v 5% 80 80 1. values given for an 8-bit bus width and a clock frequency of 26 mhz. table 4. communication channel performance multimediacard communication channel performance three-wire serial data bus (clock, command, data) variable clock rate 0, 26, 52 mhz easy card identification error protected data transfer sequential and single/multiple block oriented data transfer
device physical descriptio n nand32gah0h, nand64gah0h 8/29 3 device physical description the nandxxxah0h contains a single chip controller and flash memory module, see figure 1: device block diagram . the microcontroller interfaces with a host system allowing data to be written to and read from the flash memory module. the controller allows the host to be independent from details of erasing and programming the flash memory. figure 2 shows the package connections. see table 5: signal names for the description of the signals corresponding to the balls. figure 1. device block diagram numonyx single chip microcontroller flash module control data i/o multimediacard interface ai13614e
nand32gah0h, nand64gah0h devi ce physical description 9/29 3.1 package connections figure 2. lfbga169 package connections (top view through package) 1. the ball corresponding to v cci must be decoupled with an external capacitance. 3.2 form factor the ball diameter, d, and the ball pitch, p, for the lfbga169 package are: d = 0.30 mm (solder ball diameter) p = 0.5 mm (ball pitch) figure 3. form factor ai13626 7 11 12 13 14 h g f e d c b a 8 9 10 j 3 4 5 6 nc p n l km 2 nc nc nc nc dat3 nc nc nc v cci nc nc aa y w v u t r 1 nc nc nc v ssq nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc ab ac ad ae af ag ah dat0 dat4 nc nc nc nc nc nc nc nc nc nc nc v ccq nc dat1 dat5 v ssq nc v ccq v ccq v ssq nc nc dat2 dat6 nc v ssq cmd nc v cc v ss nc nc nc v ccq nc dat7 v ccq v cc nc clk nc v ssq nc nc nc nc v ss nc nc nc nc nc nc nc nc v ss nc nc nc nc nc nc nc nc v cc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc v ss v cc nc nc ai13627 v ssq nc v ccq nc nc d p
memory array partitioni ng nand32gah0h, nand64gah0h 10/29 4 memory array partitioning the basic unit of data transfer to/from the device is one byte. all data transfer operations which require a block size always define block lengths as integer multiples of bytes. some special functions need other partition granularity. for block oriented commands, the following definitions are used: block : the unit which is related to the block oriented read and write commands. its size is the number of bytes which are transferred when one block command is issued by the host. the size of a block is either programmable or fixed. the information about allowed block sizes and the programmability is stored in the csd register. erase group : the unit which is related to special erase and write commands defined for r/w cards. its size is the smallest number of consecutive write blocks which can be addressed for erase. the size of the erase group depends on each device and is stored in the csd. write protect group : the smallest unit that may be individually write protected. its size is defined in units of erase groups. the size of a wp-group depends on each device and is stored in the csd. figure 4 shows the nandxxxah0h memory array organization. figure 4. memory array structure 1. n = number of last erase group or last write protect group. ai13615e write protect group 0 write protect group 2 write protect group 1 write protect group n multimediacard erase group n erase group 1 erase group 0 block 0
nand32gah0h, nand6 4gah0h multimediacard interface 11/29 5 multimediacard interface the signal/pin assignments are listed in ta bl e 5 . refer to this table in conjunction with figure 2 and figure 3: form factor . 5.1 signals description 5.1.1 clock (clk) the clock input, clk, is used to synchronize the memory to the host during command and data transfers. each clock cycle gates one bit on the command and on all the data lines. the clock frequency, f pp , may vary between zero and the maximum clock frequency. 5.1.2 command (cmd) the cmd signal is a bidirectional command channel used for device initialization and command transfer. the cmd signal has two operating modes: open-drain and push-pull. the open-drain mode is used for initialization, while the push-pull mode is used for fast command transfer. commands are sent by the multimediacard bus master (or host) to the device who responds by sending back responses. 5.1.3 input/outputs (dat0-dat7) dat0 to dat7 are bidirectional data channels. the signals operate in push-pull mode. the nandxxxah0h includes internal pull ups for all data lines. these signals cannot be driven simultaneously by the host and the nandxxxah0h device. right after entering the 4-bit mode, the card disconnects the internal pull ups of lines dat1 and dat2 (dat3 internal pull up is left connected due to the spi mode cs backward compatible usage). correspondingly right after entering the 8-bit mode, the card disconnects the internal pull ups of lines dat1, dat2 and dat4-dat7. by default, after power-up or hardware reset, only dat0 is used for data transfers. the host can configure the device to use a wider data bus, dat0, dat0-dat3 or dat0-dat7, for data transfer. 5.1.4 v cc core supply voltage v cc provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). the core voltage (v cc ) can be within 2.7 v and 3.6 v. 5.1.5 v ss ground ground, v ss, is the reference for the power supply. it must be connected to the system ground.
multimediacard interfac e nand32gah0h, nand64gah0h 12/29 5.1.6 v ccq input/output supply voltage v ccq provides the power supply to the i/o pins and enables all outputs to be powered independently from v cc . the input/output voltage (v ccq ) can be either within 1.65/1.7 v and 1.95 v (low voltage range) or 2.7 v and 3.6 v (high voltage range). 5.1.7 v ssq supply voltage v ssq ground is the reference for the input/output circuitry driven by v ccq . table 5. signal names name type (1) 1. i: input; o: output, od: open drain, pp: push-pull. description dat0 i/o (pp) data dat1 i/o (pp) data dat2 i/o (pp) data dat3 i/o (pp) data dat4 i/o (pp) data dat5 i/o (pp) data dat6 i/o (pp) data dat7 i/o (pp) data cmd i/o (od or pp) command clk i (pp) clock v ccq input/output power supply v cc core power supply v ssq input/output ground v cci i must be decoupled with an external capacitance v ss ground nc nc not connected (2) 2. nc pins can be connected to ground or left floating.
nand32gah0h, nand6 4gah0h multimediacard interface 13/29 5.2 bus topology the nandxxxah0h device supports the mmc protocol. for more details, refer to section 6.4 of the jedec standard specification no. jesd84-a43. the section 12 of the jedec standard specification contains a bus circuitry diagram for reference. 5.3 power-up the power-up is handled locally in each device and in the bus master. figure 5: power-up shows the power-up sequence. refer to section 12.3 of the jedec standard specification no. jesd84-a43 for specific instructions regarding the power-up sequence. after power-up, the maximum initial load the nandxxxah0h can present on the v cc line is c4, in parallel with a minimum of r4. during operation, device capacitance on the v cc line must not exceed 10 f . 5.4 power cycling the bus master can execute any sequences of v cc and v ccq power-up/power down. however, the master must not issue any commands until v cc and v ccq are stable within each operating voltage range. for more information about power cycling see section 12.3.3 of the jedec standard specification no. jesd84-a43 and figure 6: power cycling .
multimediacard interfac e nand32gah0h, nand64gah0h 14/29 figure 5. power-up 1. the initialization sequence is a contiguous stream of logic 1? s. its length is either 1 ms, 74 clocks or the supply ramp up time, whichever is the longest. the device shall complete its init ialization within 1 second from the first cmd1 with a valid v range. 2. n cc is the number of clock cycles. 3. refer to section 7.1: operation c onditions register (ocr) for details on voltage ranges. figure 6. power cycling ai14104b supply voltage time v ccmax v ccmin (3) power-up supply ramp-up initialization sequence cmd1 cmd1 cmd1 cmd2 initialization delay cmd1 repeated until busy flag cleared (1) n cc n cc (2) v cc (3) (3) v ccqmax (3) v ccqmin (3) first cmd1 to card ready the longest of: 1 ms, 74 clock cycles, supply ramp-up time, or the boot operation period. control logic working voltage range memory field working voltage range ai14122b supply voltage time v ccmin command input prohibited v ccqmin v cc v ccq command input prohibited sleep mode
nand32gah0h, nand6 4gah0h multimediacard interface 15/29 5.5 bus operating conditions refer to section 12.6 of the jedec st andard specification no. jesd84-a43. 5.6 bus signal levels refer to section 12.6 of the jedec st andard specification no. jesd84-a43. 5.7 bus timing refer to section 12.7 of the jedec st andard specification no. jesd84-a43.
high speed multimediacard ope ration nand32gah0 h, nand64gah0h 16/29 6 high speed multimediacard operation all communication between the host and the device is controlled by the host (master). the following section provides an overview of the identification and data transfer modes, commands, dependencies, variou s operation modes and restrict ions for controlling the clock signal. for detailed information, refer to section 7 of the jedec standard specification no. jesd84-a43. 6.1 boot mode the host can read boo t data from nandxxxah0h by keeping cmd line low after power-on or sending cmd0 with argument + 0xfffffffa (optional for slave), before issuing cmd1. the data can be read from either boot area or user area depending on the register setting. refer to section 7.2 of the jedec standard specification no. jesd84-a43. 6.2 identification mode when in card identification mode, the host resets the nandxxxah0h, validates the operating voltage range and the access mode, identifies the device and assigns a relative address (rca) to it. for more information see section 7.3 of the jedec standard specification no. jesd84-a43. 6.3 data transfer mode the device enters data transfer mode once an rca is assigned to it. when the device is in standby mode, issuing the cmd7 command along with the rca, selects the device and puts it into the transfer state. the host enters data transfer mode after identifying the nandxxxah0h on the bus. when the device is in standby state, communication over the cmd and dat lines is in push-pull mode. the section 7.5 of the jedec standard specification no. jesd84-a43 contains more detailed information about data read and write, erase, write protect management, lock/unlock operations, the switch function command, high speed mode selection, and bus testing procedure. moreover section 7.5.7 contains a detailed description of the reliable write features supported by the nandxxxah0h. 6.4 clock control refer to section 7.6 of the jedec standard specification no. jesd84-a43. 6.5 error conditions refer to section 7.7 of the jedec standard specification no. jesd84-a43.
nand32gah0h, nand64gah0h high sp eed multimediacard operation 17/29 6.6 commands refer to section 7.9 of the jedec standard specification no. jesd84-a43. 6.7 state transition refer to section 7.10 and 7.12 of the jedec standard specification no. jesd84-a43. 6.8 response refer to section 7.11 of the jedec st andard specification no. jesd84-a43. 6.9 timing diagrams and values refer to section 7.14 of the jedec st andard specification no. jesd84-a43. 6.10 minimum performance refer to section 7.8 of the jedec standard specification no. jesd84-a43.
device registers na nd32gah0h, nand64gah0h 18/29 7 device registers there are five different registers within the device interface: operation conditions register (ocr) card identification register (cid) card specific data register (csd) relative card address register (rca) dsr (driver stage register) extended card specific data register (ext_csd). these registers are used for the serial data communication and can be accessed only using the corresponding commands (refer to section 7.9 of the jedec standard specification no. jesd84-a43. the device does not implement the dsr register. the multimediacard has a status register to provide information about the device current state and completion codes for the last host command. 7.1 operation conditio ns register (ocr) the 32-bit operation conditions register stores the v ccq , the input/output voltage of the flash memory component. the device is capable of communicating (identification procedure and data transfer) with any multimediacard host using any operating voltage within 1.7 v and 1.95 v (low-voltage range) or 2.7 v and 3.6 v (high-voltage range) depending on the voltage range supported by the host. for further details, refer to section 8.1 of the jedec standard specification no. jesd84-a43. if the host tries to change the ocr values duri ng an initialization pr ocedure the changes in the ocr content will be ignored. the level coding of the ocr register is as follows: restricted voltage windows = low device busy = low table 6. ocr register definition ocr bit description multimediacard 6 to 0 reserved 000 0000b 7low v ccq 1b 14 to 8 2.0 - 2.6 000 0000b 23 to 15 2.7 - 3.6 (high v ccq range) 1 1111 1111b 28 to 24 reserved 000 0000b 30 to 29 access mode 10b (sector mode) 31 power-up status bit (busy) (1) 1. this bit is set to low if the devic e has not finished the power-up routine.
nand32gah0h, nand64gah0 h device registers 19/29 7.2 card identification (cid) register the cid register is 16-byte long and contains a unique card identification number used during the card identification procedure. it is a 128-bit wide register with the content as defined in ta bl e 7 . it is programmed during device manufacturing and can not be changed by multimediacard hosts. for details, refer to section 8.2 of the jedec standard specification no. jesd84-a43. 7.3 card specific data register (csd) all the configuration information required to access the device data is stored in the csd register. the msb bytes of the register contain the manufacturer data and the two least significant bytes contains the host controlled data (the device copy, write protection and the user ecc register). the host can read the csd register and alter the host controlled data bytes using the send_csd and program_csd commands. in ta b l e 8 , the cell type column defines the csd field as read only (r), one time programmable (r/w) or erasable (r/w/e). the programmable part of the register (entries marked by w or e) can be changed by command cmd27. the copy bit in the csd can be used to mark the device as an original or a copy. once set it cannot be cleared. the device can be purchased with the copy bit set (copy) or cleared, indicating the device is a master. the one time programmable (otp) characteristic of the copy bit is implemented in the multimediacard controller firmware and not with a physical otp cell. for details, refer to section 8.3 of the jedec standard specification no. jesd84-a43. table 7. card identification (cid) register name field width cid - slice cid - value note manufacturer id mid 8 [127:120] 0xfe reserved 6 [119:114] card/bga cbx 2 [113:112] 0x01 bga oem/application id oid 8 [111:104] tbd product name pnm 48 [103:56] mmc04g, mmc08g product revision prv 8 [55:48] product serial number psn 32 [47:16] tbd manufacturing date mdt 8 [15:8] tbd crc7 checksum crc 7 [7:1] tbd not used, always ?1? ? 1 [0:0] 1
device registers na nd32gah0h, nand64gah0h 20/29 table 8. card specific data register name field width [bits] cell type csd-slice csd-value csd structure csd_structure 2 r [127:126] 2 multimediacard protocol version spec_vers 4 r [125:122] 4 reserved 2 r [121:120] tbd data read access-time-1 taac 8 r [119:112] 79 data read access-time-2 in clk cycles (nsac*100) nsac 8 r [111:104] max. data transfer rate tran_speed 8 r [103:96] 50 command classes ccc 12 r [95:84] 245 max. read data block length read_bl_len 4 r [83:80] 512 partial blocks for read allowed read_bl_partial 1 r [79:79] 1 write block misalignment write_blk_misalign 1 r [78:78] 0x00 read block misalignment read_blk_misalign 1 r [77:77] 0 dsr implemented dsr_imp 1 r [76:76] 0x00 reserved 2 r [75:74] tbd device size c_size 12 r [73:62] according to device density max. read cu rrent at v cc (min) vdd_r_curr_min 3 r [61:59] 100 ma max. read cu rrent at v cc (max) vdd_r_curr_max 3 r [58:56] 200 ma max. write cu rrent at v cc (min) vdd_w_curr_min 3 r [55:53] 100 ma max. write cu rrent at v cc (max) vdd_w_curr_max 3 r [52:50] 200 ma device size multiplier c_size_mult 3 r [49:47] according to device density erase group size erase_ grp_size 5 r [46:42] 32 erase group size multipli er erase_grp_mult 5 r [41:37] 32 write protect group size wp_grp_size 5 r [36:32] according to device density write protect group enable wp_grp_enable 1 r [31:31] 1 manufacturer default ecc default_ecc 2 r [30:29] tbd write speed factor r2w_factor 3 r [28:26] 4 max. write data block length write_bl_len 4 r [25:22] 512 partial blocks for write allowed write_bl_partial 1 r [21:21] 0 reserved [20:20] tbd content protection applicat ion content_prot_app 1 r [16:16] 0 file format group file_f ormat_group 1 r/w [15:15] 0 copy flag (otp) copy 1 r/w [14:14] 0
nand32gah0h, nand64gah0 h device registers 21/29 7.4 extended csd register the extended csd register defines the device properties and selected modes. it is 512-byte long. the 320 most significant bytes are the properties segment that defines the device capabilities and cannot be modified by the host. the 192 lower bytes are the modes segment that defines the configuration the device is working in. for details, refer to section 8.4 of the jedec standard specification no. jesd84-a43. these modes can be changed by the host by means of the switch command. permanent write protection per m_write_protect 1 r/w [13:13] 0 temporary write protection tm p_write_protect 1 r/w/e [12:12] 0 file format file_format 2 r/w [11:10] hard disk like file system with partition table ecc code 2 r/w/e none 0 ecc 2 r/w/e [9:8] 0 crc crc 7 r/w/e [7:1] tbd not used, always ?1? 1 ? [0:0] tbd table 8. card specific data register (continued) name field width [bits] cell type csd-slice csd-value table 9. extended csd (1) name field size (bytes) cell type csd-slice csd-slice value properties segment reserved (2) 7 [511:505] tbd supported command sets s_cmd_set 1 r [504] 0 reserved (2) 275 tbd [503:229] tbd boot information boot_info 1 r [228] 1 reserved (2) 1 tbd [227] tbd boot partition size boot_size_multi 1 r [226] 256 kbytes access size acc_size 1 r [225] 0 high-capacity erase unit size hc_erase_grp_size 1 r [224] 0 high-capacity erase timeout erase_timeout_mult 1 r [223] 0 reliable write sector count rel_wr_sec_c 1 r [222] 1 sector high-capacity write protect group size hc_wp_grp_size 1 r [221] 0 sleep current (v cc ) s_c_vcc 1 r [220] tbd sleep current (v ccq )s_c_vccq 1 r [219] tbd reserved (2) 1 tbd [218] tbd
device registers na nd32gah0h, nand64gah0h 22/29 sleep/awake timeout s_a_timeout 1 r [217] tbd reserved (2) 1 tbd [216] tbd sector count sec_count 4 r [215:212] according to device density reserved (2) 1 [211] tbd minimum write performance for 8 bit at 52 mhz min_perf_w_8_52 1 r [210] 8 minimum read performance for 8 bit at 52 mhz min_perf_r_8_52 1 r [209] 8 minimum write performance for 8 bit at 26 mhz, for 4 bit at 52 mhz min_perf_w_8_26_4_5 2 1 r [208] 8 minimum read performance for 8 bit at 26 mhz, for 4 bit at 52 mhz min_perf_r_8_26_4_5 2 1 r [207] 8 minimum write performance for 4 bit at 26 mhz min_perf_w_4_26 1 r [206] 8 minimum read performance for 4 bit at 26 mhz min_perf_r_4_26 1 r [205] 8 reserved (2) 1 [204] tbd power class for 26 mhz at 3.6 v pwr_cl_26_360 1 r [203] 0 power class for 52 mhz at 3.6 v pwr_cl_52_360 1 r [202] 0 power class for 26 mhz at 1.95 v pwr_cl_26_195 1 r [201] 0 power class for 52 mhz at 1.95 v pwr_cl_52_195 1 r [200] 0 reserved (2) 3 [199:197] tbd card type card_type 1 r [196] 3 reserved (2) 1 [195] tbd csd structure version csd_structure 1 r [194] 2 reserved (2) 1 [193] tbd extended csd revision ext_csd_rev 1 r [192] 2 modes segment command set cmd_set 1 r/w [191] 0 table 9. extended csd (1) (continued) name field size (bytes) cell type csd-slice csd-slice value
nand32gah0h, nand64gah0 h device registers 23/29 reserved (2) 1 [190] tbd command set revision cmd_set_rev 1 ro [189] 0 reserved (2) 1 [188] tbd power class power_class 1 r/w [187] 0 reserved (2) 1 [186] tbd high speed interface timing hs_timing 1 r/w [185] 0 reserved (2) 1 [184] tbd bus width mode bus_width 1 wo [183] 2 reserved (2) 1 [182] tbd erased memory content erased_mem_cont 1 ro [181] tbd reserved (2) 1 [180] tbd boot configuration boot_config 1 r/w [179] 0 reserved (2) 1 [178] tbd boot bus width 1 boot_bus_width 1 r/w [177] 0 reserved (2) 1 [176] tbd high-density erase group definition erase_group_def 1 r/w [175] 0 reserved (2) 175 [174:0] tbd 1. tbd stands for ?to be defined?. 2. reserved bits sh ould read as ?0?. table 9. extended csd (1) (continued) name field size (bytes) cell type csd-slice csd-slice value
device registers na nd32gah0h, nand64gah0h 24/29 7.5 rca (relative card address) register the writable 16-bit relative card a ddress (rca) register carries the device address assigned by the host during the device identification. this address is used for the addressed host-card communication after the device identification procedure. the default value of the rca register is ?0x0001?. the value ?0x0000? is reserved to set all cards into the standby state with cmd7. for details refer to section 8.5 of the jedec standard specification no. jesd84-a43. 7.6 dsr (driver stage register) register the 16-bit driver stage register (dsr) can be optionally used to improve the bus performance for extended operating conditions (depending on parameters like bus length, transfer rate or number of devices on the bus). the csd register contains the information concerning the dsr register usage. the default value of the dsr register is ?0x404?. for details refer to section 8.6 of the jedec standard specific ation no. jesd84-a43. 7.7 status register the status register provides information about the device current state and completion codes for the last host command. the device status can be explicitly read (polled) with the send_status command. the multimediacard status register structure is defined in section 7.12 of the jedec standard specification no. jesd84-a43.
nand32gah0h, nand64gah0 h package mechanical 25/29 8 package mechanical to meet environmental requirements, numonyx offers these devices in ecopack ? packages. ecopack ? packages are lead-free. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 7. lfbga169 12 x 16 x 1.4 mm 132+21+16 3r14 0.50 mm, package outline 1. drawing is not to scale. e4 e d e b sd a1 a2 a db_me ddd fd d1 e1 e2 e3 e fe se fe1 fe2 fe3 fd1 fd2 fd3
package mechanical na nd32gah0h, nand64gah0h 26/29 table 10. lfbga169 12 x 16 x 1.4 mm 132+21+16 3r14 0.50 mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.40 0.055 a1 0.15 0.006 a2 1.00 0.039 b 0.30 0.25 0.35 0.012 0.010 0.014 d 12.00 11.90 12.10 0.472 0.469 0.476 d1 6.50 0.256 ddd 0.08 0.003 e 16.00 15.90 16.10 0.630 0.626 0.634 e1 6.50 0.256 e2 10.50 0.413 e3 12.50 0.492 e4 13.50 0.531 e0.50??0.020?? fd 2.75 0.108 fd1 3.25 0.128 fd2 4.25 0.167 fd3 5.25 0.207 fe 4.75 0.187 fe1 2.75 0.108 fe2 1.75 0.069 fe3 1.25 0.049 sd 0.25 ? ? 0.010 ? ? se 0.25 ? ? 0.010 ? ?
nand32gah0h, nand64gah0 h ordering information 27/29 9 ordering information note: other digits may be added to the ordering code for preprogrammed parts or other options. devices are shipped from the factory with the memory content bits erased to ?1?. for further information on any aspect of the device, please contact your nearest numonyx sales office. table 11. ordering information scheme example: nand 32gah 0 h za 5 f device type nand flash memory density 32g = 4 gbytes 64g = 8 gbytes operating voltage a = v cc = 3.3 v, v ccq = 1.8 v or 3.3 v memory type h = emmc device options 0 = no option product version h = version h package za = lfbga169 12 x 16 x 1.4 mm temperature range 5 = ? 25 to 85 c packing e = ecopack package, standard packing f = ecopack package, tape & reel packing
revision history na nd32gah0h, nand64gah0h 28/29 10 revision history table 12. document revision history date revision changes 22-sep-2008 1 initial release. 18-nov-2008 2 document?s status promoted from ta rget specification to preliminary data. removed: density of 16 gbytes and package lfbga169 14 x 18 x 1.4 mm (zd) throughout the document. modified: ta b l e 3 : current consumption and figure 2: lfbga169 package connections (top view through package) . 04-dec-2008 3 modified figure 7: lfbga169 12 x 16 x 1.4 mm 132+21+16 3r14 0.50 mm, package outline . minor text changes.
nand32gah0h, nand64gah0h 29/29 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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